L2 Cache - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
dynwr_s Fields
Bit
13:12
page
8:4
user

L2 Cache

The MPU subsystem includes a secondary 512 KB L2 shared, unified cache memory.
Functional Description
The L2 cache is much larger than the L1 cache. The L2 cache has significantly lower latency than external
memory. The L2 cache is up to eight-way associative, configurable down to one-way (direct mapped). Like
the L1 cache, the L2 cache can be locked by cache line, locked by way, or locked by master (CPU and ACP
masters).
The L2 cache implements error correction codes (ECCs) and ECC error reporting. The cache can report a
number of events to the processor and operating system.
Related Information
Cortex-A9 MPU Subsystem Register Implementation
For more information regarding the L2 Cache Controller Address Map, refer to the Cortex-A9 MPU
Subsystem Register Implementation section.
Cache Controller Configuration
The L2 cache consists of the ARM L2C-310 L2 cache controller configured as follows:
• 512 KB total memory
• Eight-way associativity
• Physically addressed, physically tagged
• Line length of 32 bytes
• Critical first word linefills
• Support for all AXI cache modes
• Write-through
• Write-back
• Read allocate
• Write allocate
• Read and write allocate
• Single event upset (SEU) protection
• Parity on Tag RAM
• ECC on L2 Data RAM
• Two slave ports mastered by the SCU
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
Name
AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB
memory region.
This value is propagated to SCU as AWUSERS.
Description
on page 9-70
9-61
L2 Cache
Access Reset
RO 0x0
RO 0x0
Altera Corporation