Altera cyclone V Technical Reference page 660

9-24
GIC Interrupt Map for the Cyclone V SoC HPS
GIC Source Block
Interrupt
Number
193 I2C3
194 UART0
195 UART1
196 GPIO0
197 GPIO1
198 GPIO2
199 Timer0
200 Timer1
201 Timer2
202 Timer3
203 Watchdog0
204 Watchdog1
205 Clock
manager
206 Clock
manager
Altera Corporation
Interrupt Name
i2c3_IRQ
uart0_IRQ
uart1_IRQ
gpio0_IRQ
gpio1_IRQ
gpio2_IRQ
timer_l4sp_0_IRQ
timer_l4sp_1_IRQ
timer_osc1_0_IRQ
timer_osc1_1_IRQ
wdog0_IRQ
wdog1_IRQ
clkmgr_IRQ
mpuwakeup_IRQ
Combined Interrupts
This interrupt combines:
,
under_intr ic_rx_full_intr
,
ic_tx_over_intr ic_tx_
,
empty_intr ic_rd_req_intr
,
ic_tx_abrt_intr ic_rx_done_
,
intr ic_activity_intr
,
stop_det_intr ic_start_det_
, and
intr ic_gen_call_intr
—
—
—
—
—
This interrupt combines:
and .
TIMINT1 TIMINT2
This interrupt combines:
and .
TIMINT1 TIMINT2
This interrupt combines:
and .
TIMINT1 TIMINT2
This interrupt combines:
and .
TIMINT1 TIMINT2
—
—
—
—
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
Triggering
Level
ic_rx_
,
,
,
ic_
.
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
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