Functional Description Of The On-Chip Ram - Altera cyclone V Technical Reference

12-2

Functional Description of the On-Chip RAM

Figure 12-1: On-Chip RAM Block Diagram
L3 Interconnect
Note: You must initialize the on-chip RAM before you enable the ECC support to prevent false ECC
interrupts triggered by uninitialized bits.
Functional Description of the On-Chip RAM
The on-chip RAM uses an 64-bit slave interface. The slave interface supports transfers between memory
and the NIC-301 L3 interconnect. All reads and writes are serviced in order.
Related Information
Clock Manager
On-Chip RAM Clocks
The on-chip RAM is driven by the
The on-chip RAM uses an 64-bit slave interface. The slave interface supports transfers between memory
and the NIC-301 L3 interconnect. All reads and writes are serviced in order.
On-Chip RAM Resets
On-Chip RAM Initialization
You must initialize the on-chip RAM before you enable the ECC. Failure to do so triggers spurious
interrupts.
Initialize the on-chip RAM using the following steps:
• Disable ECC interrupts
• Enable ECC generation
• Initialize memory by clearing the contents by writing 0x0 in the address space
• Enable ECC interrupts
Related Information
On-Chip Memory Address Map and Register Definitions
•
• System Manager
For more information about ECC, refer to the System Manager chapter of the Cyclone V Device
Handbook.
Altera Corporation
NIC-301
Data Interface
M
ECC Register Interface
on page 2-1
l3_main_clk
on page 5-1
On-Chip RAM
S
interconnect clock.
on page 12-4
2016.10.28
ECC Error Injections
from System Manager
ECC Interrupts
to System Manager
On-Chip Memory
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