Module Reset Signals - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
The reset controller supports the following warm reset requests:
• Warm reset request pin (
• FPGA fabric
• Software warm reset request bit (
• MPU watchdog reset requests for CPU0 and CPU1
• System watchdog timer 0 and 1 reset requests
The reset controller supports the following debug reset requests:
• CDBGRSTREQ from DAP
• FPGA fabric
Figure 3-2: Reset Controller Signals
FPGA Fabric (f2h_cold_rst_req_n)
FPGA Fabric (f2h_warm_rst_req_n)
System Watchdog Reset [1:0]
FPGA Fabric (f2h_dbg_rst_req_n)

Module Reset Signals

The following tables list the module reset signals. The module reset signals are organized in groups for the
MPU, peripherals, bridges.
In the following tables, columns marked for Cold Reset, Warm Reset, and Debug Reset denote reset
signals asserted by each type of reset. For example, writing a 1 to the
resets all the modules that have a checkmark in the Warm Reset column.
Reset Manager
Send Feedback
)
nRST
POR Voltage Monitor
nPOR Pin
FPGA CB & Scan Manager
nRST Pin
MPU Watchdog Reset [1:0]
CDBGRSTREQ (DAP)
ETR
SDRAM Self-Refresh
FPGA Manager
SCAN Manager
FPGA Fabric
) of the
swwarmrstreq ctrl
Reset Controller
Cold
Module Resets
Reset
Requests
Debug Domain
TAP Domain
Warm
Reset
Requests
Debug
Reset
Requests
Reset
Handshaking
Handshaking
Inputs
Reset Manager
APB Slave Interface
Module Reset Signals
register
(Module Reset Signals)
dbg_rst_n
Reset
JTAG TAP (DAP)
Reset
MPU Clock
CPUCLKOFF[1:0]
Gating
CDBGRSTACK (DAP)
ETR
Reset
SDRAM Self-Refresh
Outputs FPGA Manager
SCAN Manager
FPGA
osc1_clk
bit in the
swwarmrstreq
3-5
register
ctrl
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