Altera cyclone V Technical Reference page 882

cv_5v4
2016.10.28
31 30
15 14
device_spare_area_size Fields
Bit
15:0
value
two_row_addr_cycles
Attached device has only 2 ROW address cycles
Module Instance
nandregs
Offset:
0x190
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
NAND Flash Controller
Send Feedback
29 28 27 26
13 12 11 10
Name
Controller will read Electronic Signature of devices
and populate this field. The PAGE512 field of the
System Manager NANDGRP_BOOTSTRAP register
will determine the value of this field to be 16.
Software could also choose to override the populated
value.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value
RW 0x0
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
two_row_addr_cycles
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB80190
21 20 19 18
5 4 3 2
13-61
17 16
1 0
Reset
RW 0x0
17 16
1 0
flag
RW 0x0
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