Altera cyclone V Technical Reference page 79

2-42
maindiv
31 30
15 14
Reserved
en Fields
Bit
9
s2fuser0clk
8
cfgclk
7
dbgtimerclk
6
dbgtraceclk
5
dbgclk
4
dbgatclk
3
l4spclk
2
l4mpclk
1
l3mpclk
0
l4mainclk
maindiv
Contains fields that control clock dividers for main clocks derived from the Main PLL Fields are only reset
by a cold reset.
Module Instance
clkmgr
Offset:
0x64
Access:
RW
Altera Corporation
29 28 27 26
13 12 11 10
Name
Enables clock s2f_user0_clk output. Qsys and user
documenation refer to s2f_user0_clk as h2f_user0_
clk.
Enables clock cfg_clk output
Enables clock dbg_timer_clk output
Enables clock dbg_trace_clk output
Enables clock dbg_clk output
Enables clock dbg_at_clk output
Enables clock l4_sp_clk output
Enables clock l4_mp_clk output
Enables clock l3_mp_clk output
Enables clock l4_main_clk output
Bit Fields
25 24 23 22
Reserved
9 8 7 6
s2fus cfgcl dbgti dbgtr
er0cl k mercl acecl
k k k
RW
RW 0x1 RW RW
0x1 0x1 0x1
Description
Base Address
0xFFD04000
21 20 19 18
5 4 3 2
dbgcl dbgat l4spc l4mpc
k clk lk lk
RW RW RW RW
0x1 0x1 0x1 0x1
Register Address
0xFFD04064
cv_5v4
2016.10.28
17 16
1 0
l3mpc l4maincl
lk k
RW RW 0x1
0x1
Access Reset
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
Clock Manager
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