Altera cyclone V Technical Reference page 587

cv_5v4
2016.10.28
Related Information
• The Global Programmers View
GPV Clocks
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FPGA-to-HPS Access to ACP
When the error correction code (ECC) option is enabled in the level 2 (L2) cache controller, all accesses
from the FPGA-to-HPS bridge to the ACP must be 64 bits wide and aligned on 8-byte boundaries after
up- or downsizing takes place. Ensure that the address alignment is a multiple of 8 bytes and that (burst
size) × (burst length) is a multiple of 8 bytes.
FPGA-to-HPS Bridge Slave Signals
The FPGA-to-HPS bridge slave address channels support user-sideband signals, routed to the ACP in the
MPU subsystem. All the signals have a fixed width except the data and write strobes for the read and write
data channels. The variable width signals depend on the data width setting of the bridge.
The following tables list all the signals exposed by the FPGA-to-HPS slave interface to the FPGA fabric.
Table 8-3: FPGA-to-HPS Bridge Slave Write Address Channel Signals
Signal
AWID
AWADDR
AWLEN
AWSIZE
AWBURST
AWLOCK
AWCACHE
AWPROT
AWVALID
AWREADY
AWUSER
Table 8-4: FPGA-to-HPS Bridge Slave Write Data Channel Signals
Signal
WID
HPS-FPGA Bridges
Send Feedback
on page 8-4
on page 8-53
Width Direction
8 bits Input
32 bits Input
4 bits Input
3 bits Input
2 bits Input
2 bits Input
4 bits Input
3 bits Input
1 bit Input
1 bit Output
5 bits Input
Width Direction
8 bits Input
FPGA-to-HPS Access to ACP
Description
Write address ID
Write address
Burst length
Burst size
Burst type
Lock type—Valid values are 00 (normal access) and
01 (exclusive access)
Cache policy type
Protection type
Write address channel valid
Write address channel ready
User sideband signals
Description
Write ID
8-5
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