Altera cyclone V Technical Reference page 96

cv_5v4
2016.10.28
Bit
8:6
can0clk
5:3
spimclk
Clock Manager
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Name
The can0_clk is divided down from the periph_base_
clk by the value specified in this field.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
The spi_m_clk is divided down from the periph_
base_clk by the value specified in this field.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Description
Description
Divide By 1
Divide By 2
Divide By 4
Divide By 8
Divide By 16
Reserved
Reserved
Reserved
Description
Divide By 1
Divide By 2
Divide By 4
Divide By 8
Divide By 16
Reserved
Reserved
Reserved
2-59
div
Access Reset
RW 0x0
RW 0x0
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