Fpga Interface Enables; Ecc And Parity Control - Altera cyclone V Technical Reference

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FPGA Interface Enables

FPGA Interface Enables
The system manager can enable or disable interfaces between the FPGA and HPS.
The global interface bit (
and HPS.
Note: Ensure that the FPGA in configured before enabling the interfaces and that all interfaces between
the FPGA and HPS are inactive before disabling them.
You can program the individual disable register (
FPGA and HPS:
You can program the FPGA interface enable registers (
between the FPGA and HPS:
• Reset request interface
• JTAG enable interface
• I/O configuration interface
• Boundary scan interface
• Debug interface
• Trace interface
• System Trace Macrocell (STM) interface
• Cross-trigger interface (CTI)
• NAND interface
• SD/MMC interface
• SPI Master interface
• EMAC interfaces

ECC and Parity Control

The system manager can enable or disable ECC for each of the following HPS modules with ECC-
protected RAM:
• MPU L2 cache data RAM
• On-chip RAM
• USB 2.0 OTG controller (USB0 and USB1) RAM
• EMAC (EMAC0 and EMAC1) RAM
• DMA controller RAM
• CAN controller RAM
• NAND flash controller RAM
• Quad SPI flash controller RAM
• SD/MMC controller RAM
• DDR interfaces
The system manager can inject single-bit or double-bit errors into the MPU L2 ECC memories for testing
purposes. Set the bits in the appropriate memory enable register to inject errors. For example, to inject a
single bit ECC error, set the
Note: The injection request is edge-sensitive, meaning that the request is latched on 0 to 1 transitions on
the injection bit. The next time a write operation occurs, the data will be corrupted, containing
Altera Corporation
) of the global disable register (
intf
bit of the
injs mpu_ctrl_l2_ecc
) disables all interfaces between the FPGA
gbl
) to disable the following interfaces between the
indiv
) to disable the following interfaces
fpgaintf_en_*
register.
cv_5v4
2016.10.28
System Manager
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