Altera cyclone V Technical Reference page 615

cv_5v4
2016.10.28
other master interfaces, connected to the HPS-to-FPGA and FPGA-to-HPS bridges, allow you to access
the GPV registers for each bridge.
The lightweight HPS-to-FPGA bridge also has a set of registers GPV to control the behavior of its four
interfaces (one slave and three masters).
The GPV allows you to set the bridge's issuing capabilities to support single or multiple transactions. The
GPV also lets you set a write tidemark through the
buffered in the bridge before data is written to slaves in the FPGA fabric.
Note: It is critical to provide correct clock settings for the lightweight HPS-to-FPGA bridge, even if your
design does not use this bridge. The
FPGA and FPGA-to-HPS bridges.
Related Information
HPS-FPGA Bridges Block Diagram and System Integration
•
Figure showing the lightweight HPS-to-FPGA bridge's three master interfaces
The Global Programmers View
•
Includes a description of the lightweight HPS-to-FPGA bridge GPV
Functional Description of the System Interconnect
•
Detailed information about connectivity, such as which masters have access to each bridge
wr_tidemark
•
Detailed information about the
AXI Bridges
•
Information about configuring the AXI bridges
Lightweight HPS-to-FPGA Bridge Master Signals
All the lightweight HPS-to-FPGA bridge master signals have a fixed width.
The following tables list all the signals exposed by the lightweight HPS-to-FPGA master interface to the
FPGA fabric.
Table 8-10: Lightweight HPS-to-FPGA Bridge Master Write Address Channel Signals
Signal
AWID
AWADDR
AWLEN
AWSIZE
AWBURST
AWLOCK
AWCACHE
AWPROT
HPS-FPGA Bridges
Send Feedback
on page 8-4
on page 7-90
wr_tidemark
on page 27-7
Width Direction
12 bits Output
21 bits Output
4 bits Output
3 bits Output
2 bits Output
2 bits Output
4 bits Output
3 bits Output
Lightweight HPS-to-FPGA Bridge Master Signals
register, to control how much data is
wr_tidemark
clock is required for GPV access on the HPS-to-
l4_mp_clk
on page 8-3
register
Write address ID
Write address
Burst length
Burst size
Burst type
Lock type—Valid values are 00 (normal access) and
01 (exclusive access)
Cache policy type
Protection type
Description
Altera Corporation
8-33