Scan Manager Block Diagram And System Integration - Altera cyclone V Technical Reference

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Scan Manager Block Diagram and System Integration

Scan Manager Block Diagram and System Integration
Figure 6-1: Scan Manager Block Diagram
(1)
Not all devices contain all the banks depicted.
System
Manager
FPGA JTAG Pins
The processor accesses the scan manager through the register slave interface connected to the level 4 (L4)
peripheral bus.
ARM JTAG-AP Signal Use in the Scan Manager
The following table describes how the ARM JTAG-AP signals are connected in the scan manager. These
signals are internal to the scan manager, are provided here for reference only, and are not shown in the
preceding figure. The signal, register, and field names listed in the table match the names used in the ARM
Debug Interface v5 Architecture Specification.
Altera Corporation
fpgajtagen
(select)
JTAG
Switch
Scan Chain 7
Scan Chain 3
Scan Chain 2
JTAG-AP
Scan Chain 1
Scan Chain 0
Register Slave Interface
FPGA Portion
Control
JTAG TAP
Block
Controller
Scan Manager
L4 Peripheral Bus (osc1_clk)
(CONFIG_IO Mode)
IOCSR
Multiplexer
IOCSR 3
IOCSR 2
IOCSR 1
IOCSR 0
cv_5v4
2016.10.28
HPS I/O Pins (1)
I/O Bank 6
I/O Bank 7A
I/O Bank 7C
I/O Bank 7B
I/O Bank 7E
I/O Bank 7D
Scan Manager
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