Functional Description Of The Clock Manager; Clock Manager Building Blocks - Altera cyclone V Technical Reference

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Functional Description of the Clock Manager

Peripheral
Quad SPI Flash
Controller
(6)
NAND Flash Controller
(Locally gated
.) (6)
clk
EMAC 0/1
SD/MMC Controller
For more information about the specific peripheral clocks, refer to their respective chapters.
Related Information
SD/MMC Controller
•
• NAND Flash Controller
Quad SPI Flash Controller
•
Ethernet Media Access Controller
•
USB 2.0 OTG Controller
•
Functional Description of the Clock Manager

Clock Manager Building Blocks

PLLs
The clock manager contains three PLLs: PLL 0 (main), PLL 1 (peripherals), and SDRAM. These PLLs
generate the majority of clocks in the HPS. There is no phase control between the clocks generated by the
three PLLs.
Clock manager provides CSR bits for software enables to some peripherals. These enables are defaulted to
(6)
enable. In boot mode, these enables are automatically active to ensure all clocks are active if RAM is cleared
for security.
Altera Corporation
pclk
hclk
ACLK
nand_mp_
mACLK
regACLK
ecc_clk
clk_x
aclk
sdmmc_clk
on page 14-1
on page 13-1
on page 15-1
on page 18-1
Clock Name
APB clock
AHB clock
AHB Data port clock
AXI Master port clock
AHB Register port clock
ECC circuitry clock
Bus Interface Clock
Application clock for DMA AXI bus and
CSR APB bus.
All registers reside in the BIU clock domain.
on page 17-1
2016.10.28
Description
Clock Manager
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