System Interconnect Address Spaces - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Figure 7-3: Interconnect Connectivity Matrix
Masters
L2 Cache Master 0
FPGA-to-HPS Bridge
DMA
EMAC 0/1
USB OTG 0/1
NAND
SD/MMC
ETR
DAP

System Interconnect Address Spaces

The system interconnect supports multiple address spaces.
Each address space uses some or all of the 4 GB address range. The address spaces overlap. Depending on
the configuration, different address spaces are visible in different regions for each master.
The following address spaces are available:
• The L3 address space
• The MPU address space
• The SDRAM address space
Available Address Maps
The following figure shows the default system interconnect address maps for all masters. The figure is not
to scale.
System Interconnect
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System Interconnect Address Spaces
Slaves
7-5
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