Altera cyclone V Technical Reference page 89

2-52
emac0clk
misc Fields
Bit
14
saten
13
fasten
12:1
bwadj
0
bwadjen
emac0clk
Contains settings that control clock emac0_clk generated from the C0 output of the Peripheral PLL. Only
reset by a cold reset.
Module Instance
clkmgr
Offset:
0x88
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
emac0clk Fields
Bit
8:0
cnt
Altera Corporation
Name
Enables saturation behavior.
Enables fast locking circuit.
Provides Loop Bandwidth Adjust value.
If set to 1, the Loop Bandwidth Adjust value comes
from the Loop Bandwidth Adjust field. If set to 0, the
Loop Bandwidth Adjust value equals the M field
divided by 2 value of the VCO Control Register. The
M divided by 2 is the upper 12 bits (12:1) of the M
field in the VCO register.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Divides the VCO frequency by the value+1 in this
field.
Description
Base Address
0xFFD04000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Access
Register Address
0xFFD04088
21 20 19 18
5 4 3 2
cnt
RW 0x1
Access
cv_5v4
2016.10.28
Reset
RW 0x1
RW 0x0
RW 0x1
RW 0x0
17 16
1 0
Reset
RW 0x1
Clock Manager
Send Feedback