Coresight Debug And Trace Block Diagram And System Integration - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
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CoreSight Debug and Trace Block Diagram and System Integration

Figure 10-1: HPS CoreSight Debug and Trace System Block Diagram
System APB
HPS JTAG Pins
CoreSight Debug and Trace
Send Feedback
CoreSight Debug and Trace Block Diagram and System Integration
PTM-0 ATB
PTM-1 ATB
To DMA
STM
Hardware Events
[31:4] [3:0]
L3 Interconnect Main Switch
L3 Interconnect
Master Peripheral Switch
HPS Debug
Configuration ROM
System AHB
DAP
Debug
APB
Debug APB
Timestamp
Generator
PTM-0 ATB
Funnel
On-Chip
0
Trace RAM
1
2
ATB ATB
3
ETF
.
.
.
7
Replicator
ATB ATB
ETR TPIU
Debug APB
I[3:2]
O[1:0] O[3:2]
csCTI
I[7:4] I[1:0]
O[5:4] O[7:6]
0
csCTM
2
1
4
CTM 1
0
CTI-0 CTI-1
PTM-0 A9-0 A9-1
Events
from FPGA
HPS Debug System
Hardware Events
CTI Triggers
To Pin
To Trace Pins [7:0]
Multiplexer &
Trace Pins
Output Trace [31:0]
To FPGA
To FPGA
FPGA-
Triggers
CTI
to/from
FPGA
MPU Debug Subsystem
MPU Debug
Configuration
ROM
PTM-1 ATB
PTM-1
10-3
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