Altera cyclone V Technical Reference page 793

cv_5v4
2016.10.28
31 30
15 14
dramifwidth Fields
Bit
7:0
ifwidth
dramsts
This register provides the status of the calibration and ECC logic.
Module Instance
sdr
Offset:
0x5038
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
SDRAM Controller Subsystem
Send Feedback
29 28 27 26
13 12 11 10
Reserved
Name
This register controls the width of the SDRAM
interface, including any bits used for ECC. For
example, for a 32-bit interface with ECC, program
this register to 0x28. The
also be programmed.
0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
ctrlwidth
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
dramsts
21 20 19 18
5 4 3 2
ifwidth
RW 0x0
Access
register must
Register Address
0xFFC25038
21 20 19 18
5 4 3 2
corrd dbeer sbeer
rop r r
RW RW RW
0x0 0x0 0x0
11-55
17 16
1 0
Reset
RW 0x0
17 16
1 0
calfa calsucce
il ss
RW RW 0x0
0x0
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