Altera cyclone V Technical Reference page 142

cv_5v4
2016.10.28
Bit
10
clkmgrcold
9
timestampcold
8
nrstpin
7
s2fcold
6
s2f
5
acpidmap
4
fpgamgr
3
sysmgrcold
2
sysmgr
1
ocram
0
rom
tstscratch
The TSTSCRATCH register is used by software as a scratch register to write and read without effecting the
reset manager function.
Module Instance
rstmgr
Offset:
0x54
Access:
RW
31 30
15 14
Reset Manager
Send Feedback
Name
Resets Clock Manager (cold reset only)
Resets debug timestamp to 0 (cold reset only)
Pulls nRST pin low
Resets logic in FPGA core that is only reset by a cold
reset (ignores warm reset) (h2f_cold_rst_n = 1)
Resets logic in FPGA core that doesn't differentiate
between HPS cold and warm resets (h2f_rst_n = 1)
Resets ACP ID Mapper
Resets FPGA Manager
Resets logic in System Manager that is only reset by a
cold reset (ignores warm reset)
Resets logic in System Manager that doesn't differen‐
tiate between cold and warm resets
Resets On-chip RAM
Resets Boot ROM
0xFFD05000
29 28 27 26
13 12 11 10
Description
Base Address
Bit Fields
25 24 23 22
field0
RW 0x0
9 8 7 6
field0
RW 0x0
tstscratch
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Register Address
0xFFD05054
21 20 19 18
5 4 3 2
3-31
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
17 16
1 0
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