Altera cyclone V Technical Reference page 237

Hard processor system
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cv_5v4
2016.10.28
an effect on the VIO channel 1 freeze signals when SRC1.VIO1 is setup to have the hardware state
machine be the freeze signal source. All fields are only reset by a cold reset (ignore warm reset).
Module Instance
sysmgr
Offset:
0x58
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
hwctrl Fields
Bit
2:1
vio1state
System Manager
Send Feedback
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Name
Software reads this field to determine the current
frozen/thawed state of the VIO channel 1 or to
determine when a freeze/thaw request is made by
writing the corresponding *REQ field in this register
has completed. Reset by a cold reset (ignores warm
reset).
Value
0x0
0x1
0x2
0x3
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Description
Description
Transitioning from thawed state to frozen
state.
Thawed state. I/Os behave as configured. I/Os
must be configured by the Scan Manager
before entering this state.
Frozen state. I/O configuration is ignored.
Instead, I/Os are in tri-state mode with a
weak pull-up. Scan Manager can be used to
configure the I/Os while they are frozen.
Transitioning from frozen state to thawed
state.
hwctrl
Register Address
0xFFD08058
21
20
19
18
5
4
3
2
vio1state
RO 0x2
Access
5-43
17
16
1
0
vio1req
RW 0x1
Reset
RO
0x2
Altera Corporation

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