Altera cyclone V Technical Reference page 863

13-42
transfer_spare_reg
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
device_reset Fields
Bit
3
bank3
2
bank2
1
bank1
0
bank0
transfer_spare_reg
Default data transfer mode. (Ignored during Spare only mode)
Module Instance
nandregs
Offset:
0x10
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Issues reset to bank 3. Controller resets the bit after
reset command is issued to device.
Issues reset to bank 2. Controller resets the bit after
reset command is issued to device.
Issues reset to bank 1. Controller resets the bit after
reset command is issued to device.
Issues reset to bank 0. Controller resets the bit after
reset command is issued to device.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFFB80000
21 20 19 18
5 4 3 2
bank3 bank2
RW RW
0x0 0x0
Access
Register Address
0xFFB80010
NAND Flash Controller
cv_5v4
2016.10.28
17 16
1 0
bank1 bank0
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Send Feedback