Altera cyclone V Technical Reference page 486

Hard processor system
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7-38
l4sp
l4sp Fields
Bit
10
sptimer1
9
can1
8
can0
7
uart1
Altera Corporation
Name
Controls whether secure or non-secure masters can
access the SP Timer 1 slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the CAN 1 slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the CAN 0 slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the UART 1 slave.
Value
0x0
0x1
Description
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
cv_5v4
2016.10.28
Access
Reset
WO
0x0
WO
0x0
WO
0x0
WO
0x0
System Interconnect
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