Altera cyclone V Technical Reference page 162

cv_5v4
2016.10.28
have completed. Software should clear DCLKSTAT.DCNTDONE before writing to the DCLKCNT register
again. This field only affects the FPGA if CTRL.EN is 1.
Module Instance
fpgamgrregs
Offset:
0x8
Access:
RW
31 30
15 14
dclkcnt Fields
Bit
31:0
cnt
dclkstat
This write one to clear register indicates that the DCLKCNT has counted down to zero. The DCLKCNT is
used by software to drive spurious DCLKs to the FPGA. Software will poll this bit after writing DCLKCNT
to know when all of the DCLKs have been sent.
Module Instance
fpgamgrregs
Offset:
0xC
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
FPGA Manager
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0xFF706000
29 28 27 26
13 12 11 10
Name
Controls DCLK counter. Software writes a non-zero
value into CNT and the FPGA Manager generates the
specified number of DCLK pulses and decrements
COUNT. This register will read back the original
value written by software. Software can write CNT at
any time.
0xFF706000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
cnt
RW 0x0
9 8 7 6
cnt
RW 0x0
Description
Base Address
dclkstat
Register Address
0xFF706008
21 20 19 18
5 4 3 2
Access
Register Address
0xFF70600C
4-19
17 16
1 0
Reset
RW 0x0
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