Altera cyclone V Technical Reference page 67

2-30
intren
Bit
3
mainplllost
2
sdrpllachieved
1
perpllachieved
0
mainpllachieved
intren
Contain fields that enable the interrupt. Fields are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0xC
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
If 1, the Main PLL has lost lock at least once since this
bit was cleared. If 0, the Main PLL has not lost lock
since this bit was cleared.
If 1, the SDRAM PLL has achieved lock at least once
since this bit was cleared. If 0, the SDRAM PLL has
not achieved lock since this bit was cleared.
If 1, the Peripheral PLL has achieved lock at least once
since this bit was cleared. If 0, the Peripheral PLL has
not achieved lock since this bit was cleared.
If 1, the Main PLL has achieved lock at least once
since this bit was cleared. If 0, the Main PLL has not
achieved lock since this bit was cleared.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Base Address
0xFFD04000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Register Address
0xFFD0400C
21 20 19 18
5 4 3 2
sdrpl perpl mainp sdrpl
llost llost lllos lachi
t eved
RW RW
0x0 0x0 RW RW
0x0 0x0
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
17 16
1 0
perpl mainplla
lachi chieved
eved
RW 0x0
RW
0x0
Clock Manager
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