Checksum Offload - Altera cyclone V Technical Reference

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LPI Timers
is configured to operate with the RGMII PHY interface operating in full-duplex mode. It cannot be used
in half-duplex mode.
EEE enables the MAC to operate in Low-Power Idle (LPI) mode. Either end point of an Ethernet link can
disable functionality to save power during periods of low link utilization. The MAC controls whether the
system should enter or exit LPI mode and communicates this information to the PHY.
Related Information
IEEE 802.3 Ethernet Working Group
For details about the IEEE 802.3az Energy Efficient Ethernet standard, refer to the IEEE 802.3 Ethernet
Working Group website.
LPI Timers
Two timers internal to the EMAC are associated with LPI mode:
• LPI Link Status (LS) Timer
• LPI Time Wait (TW) Timer
The LPI LS timer counts, in ms, the time expired since the link status has come up. This timer is cleared
every time the link goes down and is incremented when the link is up again and the terminal count as
programmed by the software is reached. The PHY interface does not assert the LPI pattern unless the
terminal count is reached. This protocol ensures a minimum time for which no LPI pattern is asserted
after a link is established with the remote station. This period is defined as one second in the IEEE
standard 802.3-az, version D2.0. The LPI LS timer is 10 bits wide, so the software can program up to 1023
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ms.
The LPI TW timer counts, in µs, the time expired since the deassertion of LPI. The terminal count of the
timer is the value of resolved transmit TW that is the auto-negotiated time after which the MAC can
resume the normal transmit operation. The LPI TW timer is 16 bits wide, so the software can program up
to 65535 µs.
The EMAC generates the LPI interrupt when the transmit or receive channel enters or exits the LPI state.

Checksum Offload

Communication protocols such as TCP and UDP implement checksum fields, which help determine the
integrity of data transmitted over a network. Because the most widespread use of Ethernet is to encapsu‐
late TCP and UDP over IP datagrams, the EMAC has a Checksum Offload Engine (COE) to support
checksum calculation and insertion in the transmit path, and error detection in the receive path.
Supported offloading types:
• Transmit IP header checksum
• Transmit TCP/UDP/ICMP checksum
• Receive IP header checksum
• Receive full checksum
Frame Filtering
The EMAC implements the following types of filtering for receive frames.
Source Address or Destination Address Filtering
The Address Filtering Module checks the destination and source address field of each incoming packet.
Altera Corporation
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2016.10.28
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Ethernet Media Access Controller
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