Altera cyclone V Technical Reference page 590

8-8
ID Register Group Register Descriptions
Register
comp_id_3 on page 8-
14
32-bit Slave
Register
fn_mod2 on page 8-15
fn_mod on page 8-16
128-bit Slave
Register
fn_mod2 on page 8-17
fn_mod on page 8-18
ID Register Group Register Descriptions
Contains registers that identify the ARM NIC-301 IP Core.
Offset:
0x1000
periph_id_4
JEP106 continuation code
periph_id_0
Peripheral ID0
periph_id_1
Peripheral ID1
periph_id_2
Peripheral ID2
periph_id_3
Peripheral ID3
comp_id_0
Component ID0
comp_id_1
Component ID1
Altera Corporation
Offset Width Acces
0x1FFC
Offset Width Acces
0x42024
0x42108
Offset Width Acces
0x44024
0x44108
on page 8-9
on page 8-9
on page 8-10
on page 8-11
on page 8-11
on page 8-12
on page 8-13
Reset Value
s
32 RO 0xB1
Reset Value
s
32 RW 0x0
32 RW 0x0
Reset Value
s
32 RW 0x0
32 RW 0x0
Description
Component ID3 Register
Description
Functionality Modification 2
Register
Issuing Functionality Modification
Register
Description
Functionality Modification 2
Register
Issuing Functionality Modification
Register
HPS-FPGA Bridges
Send Feedback
cv_5v4
2016.10.28