Altera cyclone V Technical Reference page 219

cv_5v4
2016.10.28
Offset:
0x10
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
wddbg Fields
Bit
3:2
mode_1
System Manager
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Controls behavior of L4 watchdog when CPUs in
debug mode. Field array index matches L4 watchdog
index.
Value
0x0
0x1
0x2
0x3
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Description
Continue normal operation ignoring debug
mode of CPUs
Pause normal operation only if CPU0 is in
debug mode
Pause normal operation only if CPU1 is in
debug mode
Pause normal operation if CPU0 or CPU1 is
in debug mode
wddbg
21 20 19 18
5 4 3 2
mode_1
RW 0x3
Access
RW
5-25
17 16
1 0
mode_0
RW 0x3
Reset
0x3
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