Altera cyclone V Technical Reference page 50

cv_5v4
2016.10.28
Figure 2-4: Peripheral Clock Group Divide and Gating
Peripheral
C0
PLL 1
C1
C2
C3
C4
C5
Table 2-8: Peripheral Clock Group Clocks
System Clock Name
usb_mp_clk
spi_m_clk
emac0_clk
Clock Manager
Send Feedback
emac0_base_clk
emac1_base_clk
periph_qspi_base_clk
periph_nand_sdmmc_base_clk
periph_base_clk
h2f_user1_base_clk
Frequency
Up to 200 MHz
Up to 240 MHz for the SPI
masters and up to
200 MHz for the scan
manager
Up to 250 MHz
Peripheral Clock Group
Clock Gate
Clock Gate
To Flash Controller Clocks
To Flash Controller Clocks
Divide by
Clock Gate
1, 2, 4, 8, or 16
Divide by
Clock Gate
1, 2, 4, 8, or 16
Divide by
Clock Gate
1, 2, 4, 8, or 16
Divide by
Clock Gate
1, 2, 4, 8, or 16
24-Bit
Clock Gate
Divider
Clock Gate
Divided From
Peripheral PLL C4
Peripheral PLL C4
Peripheral PLL C0
2-13
emac0_clk
emac1_clk
To main PLL group
l4_mp_clk & l4_sp_clk
multiplexer
usb_mp_clk
spi_m_clk
can0_clk
can1_clk
gpio_db_clk
h2f_user1_clock
Constraints and Notes
Clock for USB
Clock for L4 SPI master
bus and scan manager
EMAC0 clock. The
250 MHz clock is
divided internally by
the EMAC into the
typical 125/25/2.5 MHz
speeds for 1000/100/
10 Mbps operation.
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