Altera cyclone V Technical Reference page 4

TOC-4
Functional Description of the Scan Manager...........................................................................................6-5
Scan Manager Address Map and Register Definitions............................................................................6-8
Document Revision History.....................................................................................................................6-16
System Interconnect............................................................................................ 7-1
Features of the System Interconnect..........................................................................................................7-1
System Interconnect Block Diagram and System Integration............................................................... 7-2
Functional Description of the Interconnect............................................................................................. 7-4
System Interconnect Address Map and Register Definitions...............................................................7-23
Document Revision History...................................................................................................................7-134
HPS-FPGA Bridges............................................................................................. 8-1
Features of the HPS-FPGA Bridges........................................................................................................... 8-1
HPS-FPGA Bridges Block Diagram and System Integration.................................................................8-3
Functional Description of the HPS-FPGA Bridges................................................................................. 8-4
HPS-FPGA Bridges Address Map and Register Definitions................................................................8-53
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ARM JTAG-AP Scan Chains.......................................................................................................... 6-3
Configuring HPS I/O Scan Chains................................................................................................ 6-5
Communicating with the JTAG TAP Controller......................................................................... 6-6
JTAG-AP FIFO Buffer Access and Byte Command Protocol.................................................... 6-6
Clocks................................................................................................................................................ 6-7
Resets................................................................................................................................................. 6-8
JTAG-AP Register Name Cross Reference Table......................................................................... 6-8
Scan Manager Module Registers Address Map............................................................................6-9
Interconnect Block Diagram.......................................................................................................... 7-2
System Interconnect Architecture..................................................................................................7-2
Main Connectivity Matrix.............................................................................................................. 7-3
Master to Slave Connectivity Matrix............................................................................................. 7-4
System Interconnect Address Spaces.............................................................................................7-5
Master Caching and Buffering Overrides................................................................................... 7-13
Security............................................................................................................................................7-14
Controlling Quality of Service from Software............................................................................7-14
Cyclic Dependency Avoidance Schemes.....................................................................................7-15
System Interconnect Master Properties...................................................................................... 7-16
Interconnect Slave Properties.......................................................................................................7-17
Upsizing Data Width Function.................................................................................................... 7-20
Downsizing Data Width Function...............................................................................................7-21
Lock Support...................................................................................................................................7-22
FIFO Buffers and Clock Crossing................................................................................................ 7-22
System Interconnect Resets.......................................................................................................... 7-23
L3 (NIC-301) GPV Registers Address Map................................................................................7-23
The Global Programmers View...................................................................................................... 8-4
Functional Description of the FPGA-to-HPS Bridge..................................................................8-4
Functional Description of the HPS-to-FPGA Bridge............................................................... 8-19
Functional Description of the Lightweight HPS-to-FPGA Bridge..........................................8-32
Clocks and Resets...........................................................................................................................8-51
Data Width Sizing.......................................................................................................................... 8-53