Altera cyclone V Technical Reference page 796

11-58
dbecount
sbecount Fields
Bit
7:0
count
dbecount
This register tracks the double-bit error count.
Module Instance
sdr
Offset:
0x5044
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
dbecount Fields
Bit
7:0
count
erraddr
This register holds the address of the most recent ECC error.
Module Instance
sdr
Altera Corporation
Name
Reports the number of single bit errors that have
occurred since the status register counters were last
cleared.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Reports the number of double bit errors that have
occurred since the status register counters were last
cleared.
Description
Base Address
0xFFC20000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFFC20000
Access
Register Address
0xFFC25044
21 20 19 18
5 4 3 2
count
RW 0x0
Access
Register Address
0xFFC25048
SDRAM Controller Subsystem
cv_5v4
2016.10.28
Reset
RW 0x0
17 16
1 0
Reset
RW 0x0
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