Altera cyclone V Technical Reference page 811

cv_5v4
2016.10.28
31 30
Reserved
15 14
mppriority Fields
Bit
29:0
userpriority
remappriority
This register applies another level of port priority after a transaction is placed in the single port queue.
Module Instance
sdr
Offset:
0x50E0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
SDRAM Controller Subsystem
Send Feedback
29 28 27 26
13 12 11 10
Name
User Priority: This field sets the absolute user priority
of each port, which is represented as a 3-bit value. 0x0
is the lowest priority and 0x7 is the highest priority.
Port 0 is configured by programming
userpriority[2:0]
programming
configured by programming
and so on.
0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
userpriority
RW 0x0
9 8 7 6
userpriority
RW 0x0
Description
, port 1 is configured by
userpriority[5:3]
userpriority[8:6]
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
remappriority
21 20 19 18
5 4 3 2
Access
, port 2 is
,
Register Address
0xFFC250E0
21 20 19 18
5 4 3 2
priorityremap
RW 0x0
11-73
17 16
1 0
Reset
RW 0x0
17 16
1 0
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