Altera cyclone V Technical Reference page 790

11-52
dramodt
31 30
15 14
lowpwrtiming Fields
Bit
19:16
clkdisablecycles
15:0
autopdcycles
dramodt
This register controls which
with chip select 1 (CS1) assertion.
Module Instance
sdr
Offset:
0x5018
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
29 28 27 26
Reserved
13 12 11 10
Name
Set to a the number of clocks after the execution of an
self-refresh to stop the clock. This register is generally
set based on PHY design latency and should generally
not be changed.
The number of idle clock cycles after which the
controller should place the memory into power-down
mode.
pin asserts with chip select 0 (CS0) assertion and which
ODT
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
9 8 7 6
autopdcycles
RW 0x0
Description
Base Address
0xFFC20000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
cfg_read_odt_chip
RW 0x0
21 20 19 18
clkdisablecycles
5 4 3 2
Access
ODT
Register Address
0xFFC25018
21 20 19 18
5 4 3 2
cfg_write_odt_chip
SDRAM Controller Subsystem
cv_5v4
2016.10.28
17 16
RW 0x0
1 0
Reset
RW 0x0
RW 0x0
pin asserts
17 16
1 0
RW 0x0
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