Altera cyclone V Technical Reference page 972

14-26
Data Transmit
transfer expected bit (
command and the data path starts one of the following actions:
• Transmits data if the read/write bit = 1
• Receives data if read/write bit = 0
Data Transmit
The data transmit state machine starts data transmission two clock cycles after a response for the data
write command is received. This occurs even if the command path detects a response error or response
CRC error. If a response is not received from the card because of a response timeout, data is not
transmitted. Depending upon the value of the transfer mode bit (
data transmit state machine puts data on the card data bus in a stream or in blocks.
Figure 14-8: Data Transmit State Machine
Stream Data Transmit
If the
transfer_mode
path reads data from the FIFO buffer from the BIU and transmits in a stream to the card data bus. If the
FIFO buffer becomes empty, the card clock is stopped and restarted once data is available in the FIFO
†
buffer.
If the
bytcnt
data transfer, the data path continuously transmits data in a stream until the host software issues an SD/
SDIO STOP command. A stream data transfer is terminated when the end bit of the STOP command and
end bit of the data match over two clock cycles.
If the
bytcnt
to 1, the STOP command is internally generated and loaded in the command path when the end bit of the
STOP command occurs after the last byte of the stream write transfer matches. This data transfer can also
terminate if the host issues a STOP command before all the data bytes are transferred to the card bus.
Altera Corporation
) in the
data_expected
†
†
load_new_cmd,
data_expected, Write
Data & Block Transfer
Stop Data Command
Tx
Data Block
Remaining != 0
Data Not Busy
Block Done
bit in the register is set to 1, the transfer is a stream-write data transfer. The data
cmd
register is reset to 0, the transfer is an open-ended stream-write data transfer. During this
register is written with a nonzero value and the
register is set to 1, the new command is a data transfer
cmd
†
Stop Data Command
Data Tx
Idle
load_new_command,
data_expected, Write
Data & Stream Transfer
Byte Count
Byte Count
Remaining = 0
or Suspend/Stop
Data Command
Rx
CRC Status
†
send_auto_stop
†
) in the
transfer_mode
†
Tx
Data Stream
bit in the
cv_5v4
2016.10.28
register, the
cmd
register is set
cmd
†
SD/MMC Controller
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