Usb 2.0 Otg Controller Address Map And Register Definitions - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

USB 2.0 OTG Controller Address Map and Register Definitions

The address map and register definitions for the USB OTG Controller consists of the following region:
USB OTG Controller Module Registers Address Map
Registers in the USB OTG Controller Module. Only the Core Global, Power and Clock Gating, Data FIFO
Access, and Host Port registers can be accessedin both Host and Device modes. When the USB OTG
Controller is operating in one mode, either Device or Host, the application must not access registers from
the other mode. If an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the
Core Interrupt register (GINTSTS.ModeMis). When the core switches from one mode to another, the
registers in the new mode must be reprogrammed as they would be after a power-on reset. The register
address map is fixed and does not depend on the module configuration (for example, how many endpoints
are implemented). Host and Device mode registers occupy different addresses.
Related Information
Introduction to the Hard Processor System
•
The base addresses of all modules are listed in the Introduction to the Hard Processor System chapter.
http://www.altera.com/literature/hb/cyclone-v/hps.html
•
USB OTG Controller Module Registers Address Map
Registers in the USB OTG Controller Module. Only the Core Global, Power and Clock Gating, Data FIFO
Access, and Host Port registers can be accessedin both Host and Device modes. When the USB OTG
Controller is operating in one mode, either Device or Host, the application must not access registers from
the other mode. If an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the
Core Interrupt register (GINTSTS.ModeMis). When the core switches from one mode to another, the
registers in the new mode must be reprogrammed as they would be after a power-on reset. The register
address map is fixed and does not depend on the module configuration (for example, how many endpoints
are implemented). Host and Device mode registers occupy different addresses.
usb0
usb1
Global Registers
Register
gotgctl on page 18-
40
gotgint on page 18-
46
gahbcfg on page 18-
48
USB 2.0 OTG Controller
Send Feedback
Module Instance
Offset Width Acces
0x0
0x4
0x8
USB 2.0 OTG Controller Address Map and Register Definitions
on page 18-17
on page 1-1
0xFFB00000
0xFFB40000
Reset Value
s
32 RW 0x10000
32 RO 0x0
32 RW 0x0
Base Address
Description
OTG Control and Status Register
OTG Interrupt Register
AHB Configuration Register
Altera Corporation
18-17