Cortex-A9 Mpcore - Altera cyclone V Technical Reference

9-4

Cortex-A9 MPCore

Cortex-A9 MPCore
The MPU subsystem includes a stand-alone, full-featured ARM Cortex-A9 MPCore single- or dual-core
32-bit application processor. The processor, like other HPS masters, can access IP in the FPGA fabric
through the HPS-to-FPGA bridges.
Functional Description
The ARM Cortex-A9 MPCore contains the following sub-modules:
• One or two Cortex-A9 Revision r3p0 processors operating in SMP or AMP mode
• Snoop control unit (SCU)
• Private interval timer for each processor core
• Private watchdog timer for each processor core
• Global timer
• Interrupt controller
Each transaction originating from the Altera Cortex-A9 MPU subsystem can be flagged as secure or non-
secure.
Related Information
Cortex-A9 MPU Subsystem Register Implementation
For more information regarding the Cortex MPU Subsystem Address Map, refer to the Cortex-A9 MPU
Subsystem Register Implementation section.
Altera Corporation
on page 9-70
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
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