Memory Controller Architecture - Altera cyclone V Technical Reference

11-6

Memory Controller Architecture

Bus Protocol
128-bit AXI
256-bit AXI
32- or 64-bit Avalon-MM
128-bit Avalon-MM
256-bit Avalon-MM
32- or 64-bit Avalon-MM
write-only
128-bit Avalon-MM write-only
256-bit Avalon-MM write-only
32- or 64-bit Avalon-MM read-only
128-bit Avalon-MM read-only
256-bit Avalon-MM read-only
Memory Controller Architecture
The SDRAM controller consists of an MPFE, a single-port controller, and an interface to the CSRs.
Altera Corporation
Command Ports
2
2
1
1
1
1
1
1
1
1
1
Read Data Ports
2
4
1
2
4
0
0
0
1
2
4
SDRAM Controller Subsystem
cv_5v4
2016.10.28
Write Data Ports
2
4
1
2
4
1
2
4
0
0
0
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