Altera cyclone V Technical Reference page 806

11-68
protruleaddr
31 30
15 14
Reserved
protportdefault Fields
Bit
9:0
portdefault
protruleaddr
This register is used to control the memory protection for port 0 transactions. Address ranges can either be
used to allow access to memory regions or disallow access to memory regions. If TrustZone is being used,
access can be enabled for protected transactions or disabled for unprotected transactions. The default state
of this register is to allow all access. Address values used for protection are only physical addresses.
Module Instance
sdr
Offset:
0x5090
Access:
RW
Altera Corporation
29 28 27 26
13 12 11 10
Name
Determines the default action for specified transac‐
tions. When a bit is zero, the specified access is
allowed by default. When a bit is one, the specified
access is denied by default.
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
CPU write
L3 write
CPU read
L3 read
Access to FPGA-to-SDRAM port 5
Access to FPGA-to-SDRAM port 4
Access to FPGA-to-SDRAM port 3
Access to FPGA-to-SDRAM port 2
Access to FPGA-to-SDRAM port 1
Access to FPGA-to-SDRAM port 0
Base Address
0xFFC20000
21 20 19 18
5 4 3 2
portdefault
RW 0x0
Access
Register Address
0xFFC25090
SDRAM Controller Subsystem
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x0
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