Altera cyclone V Technical Reference page 64

cv_5v4
2016.10.28
ctrl Fields
Bit
2
ensfmdwr
0
safemode
bypass
Contains fields that control bypassing each PLL.
Module Instance
clkmgr
Offset:
0x4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Clock Manager
Send Feedback
Name
When set the Clock Manager will respond to a Safe
Mode request from the Reset Manager on a warm
reset by setting the Safe Mode bit. When clear the
clock manager will not set the the Safe Mode bit on a
warm reset This bit is cleared on a cold reset. Warm
reset has no effect on this bit.
When set the Clock Manager is in Safe Mode. In Safe
Mode Clock Manager register settings defining clock
behavior are ignored and clocks are set to a Safe Mode
state.In Safe Mode all clocks with the optional
exception of debug clocks, are directly generated from
the EOSC1 clock input, all PLLs are bypassed, all
programmable dividers are set to 1 and all clocks are
enabled. This bit should only be cleared when clocks
have been correctly configured This field is set on a
cold reset and optionally on a warm reset and may
not be set by SW.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
bypass
Access
RW
RW
Register Address
0xFFD04004
21 20 19 18
5 4 3 2
perpl perpl sdrpl
lsrc l lsrc
RW RW RW
0x0 0x1 0x0
2-27
Reset
0x1
0x1
17 16
1 0
sdrpl mainpll
l
RW 0x1
RW
0x1
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