Altera cyclone V Technical Reference page 838

cv_5v4
2016.10.28
31:28
Note: INT controls the value of the
the end of the DMA transfer. INT can take on one of the following values:
• 0—Do not interrupt host. The
• 1—Interrupt host. The
Data
0x0
Related Information
• Indexed Addressing
Burst DMA Command
•
Using Multi-Transaction DMA Commands
If you want the NAND flash controller DMA to perform cacheable accesses then you must configure the
cache bits by writing the
controller DMA must be idle before you use the system manager to change its cache capabilities.
You can issue non-DMA MAP10 commands while the NAND flash controller is in DMA mode. For
example, you might trigger a host-initiated page move between DMA commands, to achieve wear leveling.
However, do not interleave non-DMA MAP10 commands between the command-data pairs in a set of
multitransaction DMA commands. You must issue all four command-data pairs shown in the above tables
before sending a different command.
Note: Do not issue MAP00, MAP01 or MAP11 commands while DMA is enabled.
MAP10 commands in multitransaction format are written to the
the same as MAP10 commands in increment four (INCR4) format (described in "Burst DMA
Command").
Related Information
Indexed Addressing
•
Burst DMA Command
•
System Manager
•
Burst DMA Command
You can initiate a DMA transfer by sending a command to the NAND flash controller as a burst transac‐
tion of four 16-bit accesses. This form of DMA command might be useful for initiating DMA transfers
from custom IP in the FPGA fabric. Most processor cores cannot use this form of DMA command,
because they cannot control the width of the burst.
When DMA is enabled, the NAND flash controller recognizes the MAP10 pipeline DMA command as an
INCR4 command, in the format shown in the following table. The address decoding for MAP10 pipeline
DMA command remains the same, as shown in "MAP10 Command Format".
INT specifies the host interrupt to be generated at the end of the complete DMA transfer. For more
(34)
information about INT, see the Note at the bottom of this table.
(35) Can be only 4, 16, 32, or 64 bytes. No other values are valid.
NAND Flash Controller
Send Feedback
27:26 25:24 23:17
dma_cmd_comp
dma_cmd_comp
bit is set to 1.
dma_cmd_comp
31:16
on page 13-7
on page 13-17
register in the
l3master
on page 13-7
on page 13-17
on page 5-1
Using Multi-Transaction DMA Commands
16 15:8
bit of the
intr_status0
bit is set to 0.
15:12
0x2
group in the system manager. The NAND flash
nandgrp
Data
7:0
register in the group at
status
11:8 7:0
0x4 0x0
register at offset 0x10 in
nanddata
Altera Corporation
13-17
,