Internal Dma Controller Operations - Altera cyclone V Technical Reference

14-58

Internal DMA Controller Operations

Bits
27
26
25:9
8
7:0
Internal DMA Controller Operations
For better performance, you can use the internal DMA controller to transfer data between the host and the
controller. This section describes the internal DMA controller's initialization process, and transmission
sequence, and reception sequence.
Internal DMA Controller Initialization
To initialize the internal DMA controller, perform the following steps:
1. Set the required
• If the internal DMA controller enable bit (
DMA transfer, the change has no effect. Disabling only takes effect for a new data transfer
command.
• Issuing a software reset immediately terminates the transfer. Prior to issuing a software reset, Altera
recommends the host reset the DMA interface by setting the
†
1.
• The
multiple transaction size field (
• The
2. Write to the
guidelines:
• When a Descriptor Unavailable interrupt is asserted, the software needs to form the descriptor,
appropriately set its own bit, and then write to the poll demand register (
DMA controller to re-fetch the descriptor.
• It is always appropriate for the software to enable abnormal interrupts because any errors related to
the transfer are reported to the software.
3. Populate either a transmit or receive descriptor list in memory. Then write the base address of the first
descriptor in the list to the internal DMA controller's descriptor list base address register (
DMA controller then proceeds to load the descriptor list from memory. Internal DMA Controller
Transmission Sequences and Internal DMA Controller Reception Sequences describe this step in detail.
Related Information
Internal DMA Controller Transmission Sequences
•
Refer to this section for information about the Internal DMA Controller Transmission Sequences.
Internal DMA Controller Reception Sequences
•
Refer to this section for information about the Internal DMA Controller Reception Sequences.
Altera Corporation
Contents
RAW flag
Don't care
Register address
Don't care
Write data
register bits:
bmod
†
field of the register is read-only and a direct reflection of the contents of the DMA
pbl bmod
bit of the register has to be set appropriately for system performance.
fb bmod
register to mask unnecessary interrupt causes according to the following
idinten
†
1, if needed to read after write
0x06
Function number to abort
†
) of the
de bmod
dw_dma_multiple_transaction_size
†
†
on page 14-59
on page 14-59
Value
-
-
†
register is set to 0 during the middle of a
bit of the
dma_reset ctrl
) in the
fifoth
†
) for the internal
pldmnd
cv_5v4
2016.10.28
register to
†
register.
). The
dbaddr
†
SD/MMC Controller
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