Altera cyclone V Technical Reference page 246

5-52
persecurity
Bit
3
chansel_3
2
chansel_2
1
chansel_1
0
chansel_0
persecurity
Controls the security state of a peripheral request interface. Sampled by the DMA controller when it exits
from reset. These register bits should be updated during system initialization prior to removing the DMA
controller from reset. They may not be changed dynamically during DMA operation.
Altera Corporation
Name
Controls mux that selects whether FPGA or CAN
connects to one of the DMA peripheral request
interfaces.The peripheral request interface index
equals the array index + 4. For example, array index 0
is for peripheral request index 4.
Value
0x0
0x1
Controls mux that selects whether FPGA or CAN
connects to one of the DMA peripheral request
interfaces.The peripheral request interface index
equals the array index + 4. For example, array index 0
is for peripheral request index 4.
Value
0x0
0x1
Controls mux that selects whether FPGA or CAN
connects to one of the DMA peripheral request
interfaces.The peripheral request interface index
equals the array index + 4. For example, array index 0
is for peripheral request index 4.
Value
0x0
0x1
Controls mux that selects whether FPGA or CAN
connects to one of the DMA peripheral request
interfaces.The peripheral request interface index
equals the array index + 4. For example, array index 0
is for peripheral request index 4.
Value
0x0
0x1
Description
Description
FPGA drives peripheral request interface
CAN drives peripheral request interface
Description
FPGA drives peripheral request interface
CAN drives peripheral request interface
Description
FPGA drives peripheral request interface
CAN drives peripheral request interface
Description
FPGA drives peripheral request interface
CAN drives peripheral request interface
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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