Altera cyclone V Technical Reference page 168

cv_5v4
2016.10.28
31 30
15 14
Reserved
gpio_inten Fields
Bit
11
fpo
10
cdp
9
nsp
8
ncp
7
prd
FPGA Manager
Send Feedback
29 28 27 26
13 12 11 10
fpo cdp
RW RW
0x0 0x0
Name
Enables interrupt generation for FPGA_POWER_ON
Value
0x0
0x1
Enables interrupt generation for CONF_DONE Pin
Value
0x0
0x1
Enables interrupt generation for nSTATUS Pin
Value
0x0
0x1
Enables interrupt generation for nCONFIG Pin
Value
0x0
0x1
Enables interrupt generation for PR_DONE
Value
0x0
0x1
Bit Fields
25 24 23 22
Reserved
9 8 7 6
nsp ncp prd pre
RW RW RW RW
0x0 0x0 0x0 0x0
Description
Description
Disable Interrupt
Enable Interrupt
Description
Disable Interrupt
Enable Interrupt
Description
Disable Interrupt
Enable Interrupt
Description
Disable Interrupt
Enable Interrupt
Description
Disable Interrupt
Enable Interrupt
gpio_inten
21 20 19 18
5 4 3 2
prr ccd crc id
RW RW RW RW
0x0 0x0 0x0 0x0
Access
4-25
17 16
1 0
cd ns
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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