Altera cyclone V Technical Reference page 8

TOC-8
Document Revision History.................................................................................................................13-124
SD/MMC Controller..........................................................................................14-1
Features of the SD/MMC Controller.......................................................................................................14-1
SD/MMC Controller Block Diagram and System Integration............................................................ 14-3
SD/MMC Controller Signal Description................................................................................................ 14-4
Functional Description of the SD/MMC Controller.............................................................................14-5
SD/MMC Controller Programming Model......................................................................................... 14-39
SD/MMC Controller Address Map and Register Definitions............................................................14-84
Document Revision History.................................................................................................................14-143
Quad SPI Flash Controller................................................................................ 15-1
Features of the Quad SPI Flash Controller............................................................................................. 15-1
Quad SPI Flash Controller Block Diagram and System Integration...................................................15-2
Interface Signals......................................................................................................................................... 15-3
Functional Description of the Quad SPI Flash Controller................................................................... 15-3
Altera Corporation
NAND Controller Module Data (AXI Slave) Address Map...................................................13-33
NAND Flash Controller Module Registers (AXI Slave) Address Map.................................13-34
SD Card Support Matrix............................................................................................................... 14-2
MMC Support Matrix....................................................................................................................14-3
SD/MMC/CE-ATA Protocol........................................................................................................ 14-5
BIU................................................................................................................................................... 14-6
CIU.................................................................................................................................................14-20
Clocks............................................................................................................................................ 14-35
Resets............................................................................................................................................. 14-36
Voltage Switching.........................................................................................................................14-37
Software and Hardware Restrictions
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Initialization ................................................................................................................................ 14-41
Controller/DMA/FIFO Buffer Reset Usage..............................................................................14-47
Enabling FIFO Buffer ECC.........................................................................................................14-47
Non-Data Transfer Commands................................................................................................. 14-47
Data Transfer Commands...........................................................................................................14-49
Transfer Stop and Abort Commands........................................................................................ 14-56
Internal DMA Controller Operations....................................................................................... 14-58
Commands for SDIO Card Devices.......................................................................................... 14-60
CE-ATA Data Transfer Commands.......................................................................................... 14-62
Card Read Threshold...................................................................................................................14-70
Interrupt and Error Handling.................................................................................................... 14-73
Booting Operation for eMMC and MMC................................................................................ 14-74
SDMMC Module Address Map................................................................................................. 14-84
Overview......................................................................................................................................... 15-3
Data Slave Interface....................................................................................................................... 15-4
SPI Legacy Mode............................................................................................................................15-7
Register Slave Interface..................................................................................................................15-8
Local Memory Buffer.....................................................................................................................15-8
DMA Peripheral Request Controller...........................................................................................15-9
Arbitration between Direct/Indirect Access Controller and STIG....................................... 15-10
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....................................................................................... 14-39