Altera cyclone V Technical Reference page 347

cv_5v4
2016.10.28
MIXED2IO1 Fields
Bit
1:0
sel
MIXED2IO2
This register is used to control the peripherals connected to emac1_tx_d2 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x560
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
MIXED2IO2 Fields
Bit
1:0
sel
System Manager
Send Feedback
Name
Select peripheral signals connected emac1_mdc. 0 :
Pin is connected to GPIO/LoanIO number 55. 1 : Pin
is connected to Peripheral signal SPIS0.MOSI. 2 : Pin
is connected to Peripheral signal SPIM0.MOSI. 3 : Pin
is connected to Peripheral signal RGMII1.MDC.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected emac1_tx_d2. 0 :
Pin is connected to GPIO/LoanIO number 56. 1 : Pin
is connected to Peripheral signal SPIS0.MISO. 2 : Pin
is connected to Peripheral signal SPIM0.MISO. 3 : Pin
is connected to Peripheral signal RGMII1.TXD2.
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
MIXED2IO2
Access
Register Address
0xFFD08560
21 20 19 18
5 4 3 2
Access
5-153
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
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