Altera cyclone V Technical Reference page 101

2-64
vco
en
on page 2-71
Contains fields that control the SDRAM Clock Group enables generated from the SDRAM PLL clock
outputs. 1: The clock is enabled. 0: The clock is disabled. Fields are only reset by a cold reset.
stat
on page 2-72
Contains Output Clock Counter Reset acknowledge status.
vco
Contains settings that control the SDRAM PLL VCO. The VCO output frequency is the input frequency
multiplied by the numerator (M+1) and divided by the denominator (N+1). Fields are only reset by a cold
reset.
Module Instance
clkmgr
Offset:
0xC0
Access:
RW
31 30
regextse
l
RW 0x1
15 14
vco Fields
Bit
31
regextsel
Altera Corporation
29 28 27 26
outreset
RW 0x0
13 12 11 10
numer
RW 0x1
Name
If set to '1', the external regulator is selected for the
PLL. If set to '0', the internal regulator is slected. It is
strongly recommended to select the external regulator
while the PLL is not enabled (in reset), and then
disable the external regulater once the PLL becomes
enabled. Software should simulateously update the
'Enable' bit and the 'External Regulator Input Select'
in the same write access to the VCO register. When
the 'Enable' bit is clear, the 'External Regulator Input
Select' should be set, and vice versa. The reset value of
this bit is applied on a cold reset; warm reset has no
effect on this bit.
Base Address
0xFFD04000
Bit Fields
25 24 23 22
outre ssrc
setal
RW 0x0
l
RW
0x0
9 8 7 6
Description
Register Address
0xFFD040C0
21 20 19 18
denom
RW 0x1
5 4 3 2
pwrdn
RW
0x1
Access
cv_5v4
2016.10.28
17 16
1 0
en bgpwrdn
RW RW 0x1
0x0
Reset
RW 0x1
Clock Manager
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