Altera cyclone V Technical Reference page 105

Hard processor system

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ddrdqsclk Fields

Contains settings that control clock ddr_2x_dqs_clk generated from the C1 output of the SDRAM PLL.

Fields are only reset by a cold reset.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

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Increment the phase of the VCO output by the value

in this field multiplied by 45 degrees. The

accumulated phase shift is the total shifted amount

since the last assertion of the 'SDRAM All Output

Divider Reset' bit in the SDRAM vco control register.

In order to guarantee the phase shift to a known

value, 'SDRAM clocks output phase align' bit should

be asserted before programming this field. This field is

only writeable by SW when it is zero. HW updates

this field in real time as the phase adjustment is being

made. SW may poll this field waiting for zero

indicating the phase adjustment has completed by

Divides the VCO frequency by the value+1 in this

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

Base Address

Clock Manager

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