Altera cyclone V Technical Reference page 218

5-24
siliconid2
Bit
15:0
rev
siliconid2
Reserved for future use.
Module Instance
sysmgr
Offset:
0x4
Access:
RO
31 30
15 14
siliconid2 Fields
Bit
31:0
rsv
wddbg
Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These control registers are
used to drive the pause input signal of the L4 watchdogs. Note that the watchdogs built into the MPU
automatically are paused when their associated CPU enters debug mode. Only reset by a cold reset.
Module Instance
sysmgr
Altera Corporation
Name
Silicon revision number.
Value
0x1
0x2
0x3
29 28 27 26
13 12 11 10
Name
Reserved for future use.
Description
Description
First silicon
Silicon with L2 ECC fix
Silicon with HPS PLL (warm reset)​ fix
Base Address
0xFFD08000
Bit Fields
25 24 23 22
rsv
RO 0x0
9 8 7 6
rsv
RO 0x0
Description
Base Address
0xFFD08000
Access
Register Address
0xFFD08004
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD08010
cv_5v4
2016.10.28
Reset
RO 0x1
17 16
1 0
Reset
RO 0x0
System Manager
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