Implementation Details - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Implementation Details

Table 9-2: Cortex-A9 MPCore Processor Configuration
This table shows the parameter settings for the Altera Cortex-A9 MPCore.
Cortex-A9 processors
Instruction cache size per Cortex-A9 processor
Data cache size per Cortex-A9 processor
TLB size per Cortex-A9 processor
Media Processing Engine with NEON
per Cortex-A9 processor
Preload Engine per Cortex-A9 processor
Number of entries in the Preload Engine FIFO per
Cortex-A9 processor
Jazelle DBX extension per Cortex-A9 processor
Program Trace Macrocell (PTM) interface per
Cortex-A9 processor
Support for parity error detection
Master ports
Accelerator Coherency Port
Related Information
ARM Infocenter
For more information regarding the Cortex-A9 MPCore features and functions.
Includes support for floating-point operations.
(21)
For a description of the parity error scheme and parity error signals, refer to the Cortex-A9 Technical
(22)
Reference Manual, available on the ARM website (infocenter.arm.com).
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
Feature
technology
™
(21)
(22)
Implementation Details
Options
1 or 2
32 KB
32 KB
128 entries
Included
Included
16
Full
Included
Included
Two
Included
9-5
Altera Corporation