Altera cyclone V Technical Reference page 493

cv_5v4
2016.10.28
Bit
3
rstmgr
2
clkmgr
1
l4wd1
0
l4wd0
l4spim
Controls security settings for L4 SPIM peripherals.
Module Instance
l3regs
System Interconnect
Send Feedback
Name
Controls whether secure or non-secure masters can
access the Reset Manager slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the Clock Manager slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the L4 Watchdog Timer 0 slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the L4 Watchdog Timer 0 slave.
Value
0x0
0x1
0xFF800000
Description
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Base Address
l4spim
Access
Register Address
0xFF800018
7-45
Reset
WO 0x0
WO 0x0
WO 0x0
WO 0x0
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