Altera cyclone V Technical Reference page 979

cv_5v4
2016.10.28
Table 14-17: Non-Data Transfer Commands and Requirements
PROGRAM_CSD
(CMD27)
16
Table 14-18: Non-Data Transfer Commands and Requirements
PROGRAM_CSD
(CMD27)
16
Related Information
SD Association
•
For more information, the SD specification can be purchased from this organization.
JEDEC Global Standards of the Microelectronics Industry
•
For more information, the MMC specification can be purchased from this organization.
Clock Control Block
The clock control block provides different clock frequencies required for SD/MMC/CE-ATA cards. The
clock control block has one clock divider, which is used to generate different card clock frequencies.
The clock frequency of a card depends on the following clock
•
clkdiv
the cards. The division factor for the clock divider can be set by writing to the
clock divider is an 8-bit value that provides a clock division factor from 1 to 510; a value of 0 represents
a clock-divider bypass, a value of 1 represents a divide by 2, a value of 2 represents a divide by 4, and so
†
on.
•
clksrc
•
clkena
conditions:
•
cclk_out
set to 0.
• Low-power mode can be enabled by setting the
low-power mode is enabled to save card power, the
for at least eight card clock cycles. Low-power mode is enabled when a new command is loaded and
the command path goes to a non-idle state.
Under the following conditions, the card clock is stopped or disabled:
(48) Num_bytes = Number of bytes specified as per the lock card data structure. Refer to the SD specification and
the MMC specification.
Num_bytes = Number of bytes specified as per the lock card data structure. Refer to the SD specification and
(49)
the MMC specification.
SD/MMC Controller
Send Feedback
SEND_WRITE_ LOCK_UNLOCK
PROT (CMD30)
Block Size register programing
4 Num_bytes
SEND_WRITE_ LOCK_UNLOCK
PROT (CMD30)
Byte Count register programming
4 Num_bytes
register—Internal clock dividers are used to generate different clock frequencies required for
register—Set this register to 0 as clock is divided by clock divider 0.
register—The card output clock can be enabled or disabled under the following
cclk_out
†
is enabled when the
†
†
†
†
SD_
(CMD42) STATUS
(ACMD13)
64
(48)
†
SD_
(CMD42) STATUS
(ACMD13)
64
(49)
bit in the
cclk_enable clkena
cclk_low_power
cclk_out
†
Clock Control Block
SEND_NUM_WR_ SEND_SCR (ACMD51)
BLOCKS (ACMD22)
†
4 8
SEND_NUM_WR_ SEND_SCR (ACMD51)
BLOCKS (ACMD22)
†
4 8
†
register settings:
ctrl
clkdiv
†
register is set to 1 and disabled when
bit of the
clkena
signal is disabled when the card is idle
†
14-33
†
register. The
register to 1. If
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