Altera cyclone V Technical Reference page 938

cv_5v4
2016.10.28
Bit
7
uncor_err_b2
6:0
max_errors_b2
DMA registers Register Descriptions
Offset:
0x700
dma_enable
dma_intr
on page 13-118
DMA interrupt register
dma_intr_en
Enables corresponding interrupt bit in dma interrupt register
target_err_addr_lo
Transaction address for which controller initiator interface received an ERROR target response.
target_err_addr_hi
Transaction address for which controller initiator interface received an ERROR target response.
flash_burst_length
chip_interleave_enable_and_allow_int_reads
no_of_blocks_per_lun
lun_status_cmd
Indicates the command to be sent while checking status of the next LUN.
dma_enable
Module Instance
nandregs
Offset:
0x700
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
NAND Flash Controller
Send Feedback
Name
Uncorrectable error occurred while reading pages for
last transaction in Bank2. Uncorrectable errors also
generate interrupts in intr_statusx register.
Maximum of number of errors corrected per sector in
Bank2. This field is not valid for uncorrectable errors.
A value of zero indicates that no ECC error occurred
in last completed transaction.
on page 13-117
on page 13-119
on page 13-119
on page 13-120
on page 13-120
on page 13-122
on page 13-123
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
DMA registers Register Descriptions
Description
on page 13-121
Base Address
0xFFB80700
13-117
Access Reset
RO 0x0
RO 0x0
Register Address
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