Peripheral Request Interface - Altera cyclone V Technical Reference

16-10
Issuing Instructions to the DMAC using a Slave Interface
Issuing Instructions to the DMAC using a Slave Interface
When the DMAC is operating, you can only issue the following instructions:
• —Starts a DMA transaction using a DMA channel that you specify
DMAGO
•
DMASEV
•
DMAKILL
You must ensure that you use the appropriate slave interface, depending on the security state in which the
boot_manager_ns
issue the instruction using the secure slave interface, otherwise the DMAC ignores the instruction. You
can use the secure or non-secure slave interface to start or restart a DMA channel when the DMAC is in
the non-secure state.
Note: Before you can issue instructions using the debug instruction registers or the
must read the
instructions.
The DMAC immediately processes any instructions received from a slave interface, unless the pipeline is
busy processing another instruction.
Note: Prior to issuing
the DMAC to execute, starting at the address that the
Using DMAGO with the Debug Instruction Registers
The following example shows the necessary steps to start a DMA channel thread using the debug instruc‐
tion registers:
1. Create a program for the DMA channel.
2. Store the program in a region of system memory.
3. Program one of the slave interfaces on the DMAC to a
a. Poll the
b. Write to the
• Instruction byte 0 encoding for
• Instruction byte 1 encoding for
• Debug thread bit to 0 to select the DMA manager thread
c. Write to the
bytes to the address of the first instruction in the program that is written to system memory in
2
above.
4. Instruct the DMAC to execute the instruction that the debug instruction registers contain by writing
zero to the
After the DMAC completes execution of the instruction, it clears the

Peripheral Request Interface

The following figure shows that the peripheral request interface consists of a peripheral request bus and a
DMAC acknowledge bus that use the prefixes:
• —The peripheral request bus
dr
• —The DMAC acknowledge bus
da
Altera Corporation
—Signals the occurrence of an event, or interrupt, using an event number that you specify
—Terminates a thread
signal initializes the DMAC. For example, if the DMAC is in the secure state, you must
register to ensure that debug is idle, otherwise the DMAC ignores the
DBGSTATUS
, you must ensure that the system memory contains a suitable program for
DMAGO
register to ensure that debug is idle, and the
DBGSTATUS
register and enter all of the following:
DBGINST0
register with the
DBGINST1
register. The DMAC starts the DMA channel thread and sets the
DBGCMD
DMAGO
instruction as follows:
DMAGO
DMAGO
DMAGO
instruction byte [5:2] data. You must set these four
DMAGO
DBGCMD
specifies.
bit is 0.
dbgstatus
dbgstatus
bit to 0.
dbgstatus
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2016.10.28
register, you
step
bit to 1.
DMA Controller